Performance models for computer systems are widely used to evaluate
architectural tradeoffs early in the design cycle and to project the
behavior of a given workload on a proposed architecture. Such models
typically rely on a high-level abstraction of system components and the way
they interact with a given workload. A simple example is a collection of
cache miss rates used to (partially) describe the memory system. In this
work we propose an abstraction of processor behavior. Our goal is to discern
the main attributes of overlapping cache misses with each other and with
other useful work. Our basic constructs are the probability distributions of
the miss interarrival times and the times between the miss and the
corresponding processor stall. It will be seen that the proposed abstraction
results in errors of only up to 3 percent as compared with cycle accurate
simulation. Furthermore, we will show that the constructs are latency
invariant. This allows one to model a variety of system interconnects which
typically have many different levels of latency.